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june 2006 rev 7 1/41 1 m95128 m95128-w m95128-r 128 kbit serial spi bus eeprom with high speed clock feature summary compatible with spi bu s serial interface (positive clock spi modes) single supply voltage: ? 4.5 to 5.5v for m95128 ? 2.5 to 5.5v for m95128-w ? 1.8 to 5.5v for m95128-r high speed ? 5mhz clock rate, 5ms write time status register hardware protection of the status register byte and page write (up to 64 bytes) self-timed programming cycle adjustable size re ad-only eeprom area enhanced esd protection more than 100,000 write cycles more than 40-year data retention packages ? ecopack? (rohs compliant) so8 (mn) 150 mil width tssop8 (dw) 169 mil width www.st.com
contents m95128, m95128-w, m95128-r 2/41 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.3 internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.3 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
m95128, m95128-w, m95128-r contents 3/41 5.6.1 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . 22 6 delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables m95128, m95128-w, m95128-r 4/41 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. operating conditions (m95128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. operating conditions (m95128-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 table 9. operating conditions (m95128-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. dc characteristics (m95128, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. dc characteristics (m95128-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. dc characteristics (m95128-w, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15. dc characteristics (m95128-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 16. ac characteristics (m95128, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17. ac characteristics (m95128-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 18. ac characteristics (m95128-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 19. ac characteristics (m95128-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 20. so8n ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 21. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . 37 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
m95128, m95128-w, m95128-r list of figures 5/41 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. so and tssop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 6. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18. so8n ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 36 figure 19. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 37
summary description m95128, m95128-w, m95128-r 6/41 1 summary description these electrically erasable programmable memory (eeprom) devices are accessed by a high speed spi-compatible bus. the memory array is organized as 16384 x 8 bits. the device is accessed by a simple serial interface that is spi-compatible. the bus signals are c, d and q, as shown in ta b l e 1 and figure 1 . the device is selected when chip select (s ) is taken low. communications with the device can be interrupted using hold (hold ). in order to meet environmental requirements, st offers these devices in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 1. logic diagram figure 2. so and tssop connections 1. see section 10: package mechanical for package dimensions, and how to identify pin-1. ai12805 s v cc m95128 hold v ss w q c d d v ss c hold q sv cc w ai12806 m95128 1 2 3 4 8 7 6 5
m95128, m95128-w, m95128-r summary description 7/41 table 1. signal names c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground
memory organization m95128, m95128-w, m95128-r 8/41 2 memory organization the memory is organized as shown in figure 3 . figure 3. block diagram ai01272c hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register
m95128, m95128-w, m95128-r signal description 9/41 3 signal description see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 3.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 3.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). 3.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) ch anges after the fa lling edge of serial clock (c). 3.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the standby power mode. driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 3.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select (s ) driven low.
signal description m95128, m95128-w, m95128-r 10/41 3.6 write protect (w ) the main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write instructions. 3.7 supply voltage (v cc ) 3.7.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage must be applied: this voltage must be a dc voltage within the specified [v cc (min), v cc (max)] range, as defined in ta b l e 7 , ta bl e 8 and ta bl e 9 . in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10nf to 100nf) close to the v cc /v ss package pins. the v cc voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 3.7.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s ) signal is not allowed to float and must follow the v cc voltage. the s line should therefore be connected to v cc via a suitable pull-up resistor. in addition, the chip select (s ) input offers a built-in safety feature, as it is both edge sensitive and level sensitive. practically this means that after power-up, the device cannot become selected until a fa lling edge has first been det ected on chip select (s ). so the chip select (s ) signal must first have been high and then gone low before the first operation can be started. 3.7.3 internal device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device will not respond to any instruction until the v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in section 9: dc and ac parameters ). when v cc has passed the por threshold voltage, the device is reset and in the following state: in standby power mode deselected (at next power-up, a falling edge is required on chip select (s ) before any instructions can be executed) not in the hold condition status register state: ? the write enable latch (wel) bit is reset to 0 ? the write in progress (wip) bit is reset to 0. the srwd, bp1 and bp0 bits of the status register are at the same logic level as when the device was last powered down (they are non-volatile bits).
m95128, m95128-w, m95128-r operating features 11/41 3.7.4 power-down at power-down, the device must be deselected and in standby power mode (that is, there should be no internal write cycl e in progress). chip select (s ) should be allowed to follow the voltage applied on v cc . 4 operating features 4.1 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device must be selected, with chip select (s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold (hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in figure 4 ). the hold condition ends when the hold (hold ) signal is driven high at the same time as serial clock (c) already being low. figure 4 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. figure 4. hold condition activation ai02029d hold c hold condition hold condition
operating features m95128, m95128-w, m95128-r 12/41 4.2 status register figure 3 shows the position of the status register in the control logic of the device. the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. for a detailed description of the status register bits, see section 5.3: read stat us register (rdsr) . 4.3 data protection and protocol control non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. consequently, the device features the following data protection mechanisms: write and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? write (write) instruction completion the block protect (bp1, bp0) bits allow part of the memory to be configured as read- only. this is the software protected mode (spm). the write protect (w ) signal allows the block protect (bp1, bp0) bits to be protected. this is the hardware protected mode (hpm). for any instruction to be accepted, and executed, chip select (s ) must be driven high after the rising edge of serial clock (c) for the last bit of the instruction, and before the next rising edge of serial clock (c). two points need to be noted in the previous sentence: the ?last bit of the instruction? can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for read status register (rdsr) and read (read) instructions). the ?next rising edge of serial clock (c)? might (or might not) be the next bus transaction for some other device on the spi bus. table 2. write-protected block size status register bits protected block array addresses protected bp1 bp0 m95128, m95128-w, m95128-r 0 0 none none 0 1 upper quarter 3000h - 3fffh 1 0 upper half 2000h - 3fffh 1 1 whole memory 0000h - 3fffh
m95128, m95128-w, m95128-r instructions 13/41 5 instructions each instruction starts with a sing le-byte code, as summarized in ta bl e 3 . if an invalid instruction is sent (one not contained in ta b l e 3 ), the device automatically deselects itself. 5.1 write enable (wren) the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 5 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) being driven high. figure 5. write enable (wren) sequence table 3. instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 c d ai02281e s q 2 1 34567 high impedance 0 instruction
instructions m95128, m95128-w, m95128-r 14/41 5.2 write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 6 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be dese lected, by chip select (s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: power-up wrdi instruction execution wrsr instruction completion write instruction completion. figure 6. write disable (wrdi) sequence c d ai03750d s q 2 1 34567 high impedance 0 instruction
m95128, m95128-w, m95128-r instructions 15/41 5.3 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 7 . the status and control bits of the status register are as follows: 5.3.1 wip bit the write in progress (wip) bit indicates whet her the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 5.3.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write status register instruction is accepted. 5.3.3 bp1, bp0 bits the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta bl e 4 ) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. 5.3.4 srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. table 4. status register format b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
instructions m95128, m95128-w, m95128-r 16/41 figure 7. read status register (rdsr) sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m95128, m95128-w, m95128-r instructions 17/41 5.4 write status register (wrsr) the write status register (wrsr) instruction a llows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruct ion is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 8 . the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. chip select (s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read- only, as defined in ta b l e 4 . the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered. the contents of the status register write disable (srwd) and block protect (bp1, bp0) bits are frozen at their current values from just before the start of the execution of write status register (wrsr) instruction. the new, updated, values take effect at the moment of completion of the execution of write status register (wrsr) instruction.
instructions m95128, m95128-w, m95128-r 18/41 the protection features of the device are summarized in ta bl e 2 . when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in struction, regardless of the whether write protect (w ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w ): if write protect (w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. if write protect (w ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: by setting the status register write disabl e (srwd) bit after driving write protect (w ) low or by driving write protect (w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w ) high. if write protect (w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, can be used. table 5. protection modes w signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protect ( bp1, bp0) bits of the status register, as shown in table 5 . unprotected area (1) 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the bp1 and bp0 bits can be changed write protected ready to accept write instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the bp1 and bp0 bits cannot be changed write protected ready to accept write instructions
m95128, m95128-w, m95128-r instructions 19/41 figure 8. write status register (wrsr) sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
instructions m95128, m95128-w, m95128-r 20/41 5.5 read from memory array (read) as shown in figure 9 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. when the highest address is reached, the addr ess counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. figure 9. read from memory array (read) sequence 1. the most significant address bits (b15, b14) are don?t care. c d ai01793d s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 76543 1 7 0 high impedance data out 1 instruction 16-bit address 0 msb msb 2 31 data out 2
m95128, m95128-w, m95128-r instructions 21/41 5.6 write to memory array (write) as shown in figure 10 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select (s ) high at a byte boundary of the input data. in the case of figure 10 , this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is be ing used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ta bl e 1 6 to ta b l e 1 9 ), at the end of which the write in progress (wip) bit is reset to 0. if, though, chip select (s ) continues to be driven low, as shown in figure 11 , the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (the page size of these devices is 64 bytes). the instruction is not accepted, and is not executed, under the following conditions: if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by chip select (s ) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. figure 10. byte write (write) sequence 1. the most significant address bits (b15, b14) are don?t care. c d ai01795d s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 high impedance instruction 16-bit address 0 765432 0 1 data byte 31
instructions m95128, m95128-w, m95128-r 22/41 figure 11. page write (write) sequence 1. the most significant address bits (b15, b14) are don?t care. 5.6.1 ecc (error correcti on code) and write cycling the m95128 (5v version, processed in f6dp26%, identified with letter "v") offers an ecc (error correction code) logic which compares each 4-byte packet with its associated ecc word (6 eeprom bits). as a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ecc detects it and replaces it by the correct value. the read reliability is th erefore much improved by the use of this feature. note however that even though a single byte has to be written, 4 bytes are internally modified (plus the ecc word), that is, the addressed byte is cycled together with the three other bytes making up the packet. it is therefore recommended to write by packets of 4 bytes in order to benefit from the larger amount of write cycles. the maximum number of write cycles for the m95128 device (5v ve rsion, processed in f6dp26%, identified with letter "v") is qualified as 100,000 write cycles, using a cycling routine that writes to the device page by page (that is, by multiples of 4-byte packets). the m95128-w and m95128-r devices (2.5v and 1.8v versions, processed in f6dp36% and identified with the letter "a") do not offer the ecc logic and are qualified for a maximum number of 100,000 write cycles. c d ai01796d s 34 33 35 36 37 38 39 40 41 42 44 45 46 47 32 c d s 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 instruction 16-bit address 0 765432 0 1 data byte 1 31 43 765432 0 1 data byte 2 765432 0 1 data byte 3 65432 0 1 data byte n
m95128, m95128-w, m95128-r delivery state 23/41 6 delivery state the device is delivered with the memory array set at all 1s (ffh). the status register write disable (srwd) and block protect (bp1 and bp0) bits are initialized to 0. 7 connecting to the spi bus these devices are fully compatible with the spi protocol. all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s ) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 12 shows three devices, connected to an mcu, on a spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, all the others being high impedance. figure 12. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, hi gh or low as appropriate. 2. these pull-up resistors, r, ensur e that the m95128, m95128-w, m95128-r are not selected if the bus master leaves the s line in the high-impedance state. as the bus master may enter a state where all inputs/outputs are in high impedance at the same time (that is when the bus master is reset), the clock line (c) mu st be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, s is pulled high while c is pul led low (thus ensuring that s and c do not become high at the same time, and so, that the t shch requirement is met). ai12304b bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold r (2) r (2) r (2) v cc v cc v cc v cc v ss v ss v ss v ss r (2)
connecting to the spi bus m95128, m95128-w, m95128-r 24/41 7.1 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from th e falling edge of serial clock (c). the difference between the two modes, as shown in figure 13 , is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 13. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
m95128, m95128-w, m95128-r maximum rating 25/41 8 maximum rating stressing the device outside the ratings listed in ta bl e 6 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (1) 1. aec-q100-002 (compliant with jedec std jesd22-a114a, c1=100pf, r1=1500w, r2=500 ? ). ?4000 4000 v
dc and ac parameters m95128, m95128-w, m95128-r 26/41 9 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 7. operating conditions (m95128) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (device grade 3) ?40 125 c table 8. operating conditions (m95128-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 9. operating conditions (m95128-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c
m95128, m95128-w, m95128-r dc and ac parameters 27/41 figure 14. ac measurement i/o waveform table 10. ac measurement conditions (1) 1. output hi-z is defined as the point where data out is no longer driven. symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v table 11. capacitance (1) 1. sampled only, not 100% tested, at t a =25c and a frequency of 5 mhz. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (d) v in = 0v 8 pf input capacitance (other pins) v in = 0v 6 pf ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
dc and ac parameters m95128, m95128-w, m95128-r 28/41 table 12. dc characteristics (m95128, device grade 3) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 5 mhz, v cc = 5 v, q = open 4ma i cc1 supply current (standby power mode) s = v cc , v cc = 5 v, v in = v ss or v cc 5a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol (1) 1. for all 5v range devices, the dev ice meets the output requirements for both ttl and cmos standards. output low voltage i ol = 2 ma, v cc = 5 v 0.4 v v oh (1) output high voltage i oh = ?2 ma, v cc = 5 v 0.8 v cc v table 13. dc characteristics (m95128-w, device grade 6) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current (read) c = 0.1v cc /0.9v cc at 5mhz, v cc = 2.5v, q = open 3ma c = 0.1v cc /0.9v cc at 5mhz, v cc = 5v, q = open 5ma i cc0 (1) 1. characterized value, not tested in production. supply current (write) during t w , s = v cc , 2.5v < v cc < 5.5v 5ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , 2.5v < v cc < 5.5v 5a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage v cc = 2.5v and i ol = 1.5ma or v cc = 5v and i ol = 2ma 0.4 v v oh output high voltage v cc = 2.5v and i oh = ?0.4ma or v cc = 5v and i oh = ?2ma 0.8 v cc v
m95128, m95128-w, m95128-r dc and ac parameters 29/41 table 14. dc characteristics (m95128-w, device grade 3) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current (read) c = 0.1v cc /0.9v cc at 5mhz, v cc = 2.5v, q = open 3ma i cc0 (1) 1. characterized value, not tested in production. supply current (write) during t w , s = v cc , 2.5v < v cc < 5.5v 6ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc 2.5v < v cc < 5.5v, 5a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage v cc = 2.5v and i ol = 1.5ma or v cc = 5v and i ol = 2ma 0.4 v v oh output high voltage v cc = 2.5v and i oh = ?0.4ma or v cc = 5v and i oh = ?2ma 0.8 v cc v table 15. dc characteristics (m95128-r) symbol parameter test condition min max unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current (read) c = 0.1v cc /0.9v cc at 2 mhz, v cc = 1.8 v, q = open 1 (1) 1. this is preliminary data. ma i cc0 (2) 2. characterized value, not tested in production. supply current (write) during t w , s = v cc , 1.8v < v cc < 5.5v 3ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , 1.8v < v cc < 5.5v 3 (1) a v il input low voltage ?0.45 0.25 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v 0.8 v cc v
dc and ac parameters m95128, m95128-w, m95128-r 30/41 table 16. ac characteristics (m95128, device grade 3) test conditions specified in table 10 and table 7 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 ns t cl (1) t cll clock low time 90 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t clhl clock low set-up time before hold active 0 ns t clhh clock low set-up time before hold not active 0 ns t shqz (2) t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 50 ns t qhql (2) t fo output fall time 50 ns t hhqv t lz hold high to output valid 50 ns t hlqz (2) t hz hold low to output high-z 100 ns t w t wc write time 5 ms
m95128, m95128-w, m95128-r dc and ac parameters 31/41 table 17. ac characteristics (m95128-w, device grade 6) test conditions specified in table 10 and table 8 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 ns t cl (1) t cll clock low time 90 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t clhl clock low set-up time before hold active 0 ns t clhh clock low set-up time before hold not active 0 ns t shqz (2) t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 50 ns t qhql (2) t fo output fall time 50 ns t hhqv t lz hold high to output valid 50 ns t hlqz (2) t hz hold low to output high-z 100 ns t w t wc write time 5 ms
dc and ac parameters m95128, m95128-w, m95128-r 32/41 table 18. ac characteristics (m95128-w, device grade 3) test conditions specified in table 10 and table 8 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 ns t cl (1) t cll clock low time 90 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t clhl clock low set-up time before hold active 0 ns t clhh clock low set-up time before hold not active 0 ns t shqz (2) t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 50 ns t qhql (2) t fo output fall time 50 ns t hhqv t lz hold high to output valid 50 ns t hlqz (2) t hz hold low to output high-z 100 ns t w t wc write time 5 ms
m95128, m95128-w, m95128-r dc and ac parameters 33/41 table 19. ac characteristics (m95128-r) test conditions specified in table 10 and table 9 symbol alt. parameter min. (1) 1. this is preliminary data. max. (1) unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 200 ns t shch t css2 s not active setup time 200 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 200 ns t chsl s not active hold time 200 ns t ch (2) 2. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 200 ns t cl (2) t cll clock low time 200 ns t clch (3) 3. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (3) t fc clock fall time 1 s t dvch t dsu data in setup time 40 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 140 ns t hlch clock low hold time after hold active 90 ns t clhl clock low set-up time before hold active 0 ns t clhh clock low set-up time before hold not active 0ns t shqz (3) t dis output disable time 250 ns t clqv t v clock low to output valid 150 ns t clqx t ho output hold time 0 ns t qlqh (3) t ro output rise time 100 ns t qhql (3) t fo output fall time 100 ns t hhqv t lz hold high to output valid 100 ns t hlqz (3) t hz hold low to output high-z 250 ns t w t wc write time 10 ms
dc and ac parameters m95128, m95128-w, m95128-r 34/41 figure 15. serial input timing figure 16. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai01448b s d hold tclhl thlch thhch tclhh thhqv thlqz
m95128, m95128-w, m95128-r dc and ac parameters 35/41 figure 17. output timing c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
package mechanical m95128, m95128-w, m95128-r 36/41 10 package mechanical figure 18. so8n ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 20. so8n ? 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
m95128, m95128-w, m95128-r package mechanical 37/41 figure 19. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. table 21. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
part numbering m95128, m95128-w, m95128-r 38/41 11 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 22. ordering information scheme example: m95128 ? w mn 6 t p /p device type m95 = spi serial access eeprom device function 128 = 128 kbit (16384 x 8) operating voltage blank = v cc = 4.5 to 5.5v (1) 1. the m95128 5v part is offered in "v" process (f6dp26%) only. w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v package mn = so8 (150 mils width) dw = tssop8 (169 mils width) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 = device tested with high reliability certified flow (2) automotive temperature range (?40 to 125 c) 2. st strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliability certified flow (hrcf) is des cribed in the quality note qnee9801. please ask your nearest st sales office for a copy. option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = ecopack? (rohs compliant) process p = f6dp26% chartered v = f6dp26% rsst
m95128, m95128-w, m95128-r revision history 39/41 12 revision history table 23. document revision history date revision changes 17-nov-1999 2.1 new -v voltage range added (including the tables for dc characteristics, ac characteristics, and ordering information). 07-feb-2000 2.2 new -v voltage range extended to m95256 (including ac characteristics, and ordering information). 22-feb-2000 2.3 tclch and tchcl, for the m95xxx-v, changed from 1 s to 100ns 15-mar-2000 2.4 -v voltage range changed to 2.7-3.6v 29-jan-2001 2.5 lead soldering temperature in the absolute maximum ratings table amended illustrations and package mechanical data updated 12-jun-2001 2.6 correction to header of table 12b tssop14 illustrations and pa ckage mechanical data updated document promoted from preliminary data to full data sheet 08-feb-2002 2.7 announcement made of planned upgrade to 10 mhz clock for the 5v, ?40 to 85c, range. 09-aug-2002 2.8 m95128 split off to its own datasheet. data added for new and forthcoming products, including availability of the so8 narrow package. 24-feb-2003 2.9 omission of so8 narrow package mechanical data remedied 26-jun-2003 2.10 -v voltage range removed 21-nov-2003 3.0 table of contents, and pb-free options added. -s voltage range extended to -r. v il (min) improved to ?0.45v 17-mar-2004 4.0 absolute maximum ratings for v io (min) and v cc (min) changed. soldering temperature information clarified for rohs compliant devices. device grade information clarified 21-oct-2004 5.0 m95128 datasheet merged back in. product list summary table added. aec-q100-002 compliance. device grade information clarified. thhqx corrected to thhqv. 10mhz product becomes standard
revision history m95128, m95128-w, m95128-r 40/41 13-apr-2006 6 new m95128 datasheet extracted from the m95128/256 datasheet. order of sections modified. ecc (error correction code) and write cycling paragraph added. section 3.7: supply voltage (v cc ) added and information removed below section 4: operating features . power up state removed below section 6: delivery state . figure 13: spi modes supported modified and note 2 added. i cc1 specified over the whole v cc range and i cc0 added to ta bl e 1 3 , ta b l e 1 4 and ta b l e 1 5 . i cc specified over the whole v cc range in ta b l e 1 3 . t chhl and t chhh replaced by t clhl and t clhh , respectively. figure 16: hold timing modified. process letter and note 1 added to table 22: ordering information scheme . ? ac characteristics (m95128, device grade 6) ? table (for 10mhz frequency) removed. note 1 removed from table 19: ac characteristics (m95128-r) . t a added to table 6: absolute maximum ratings . pdip8 (bn) and so8 wide (mw) packages removed. m95128-w and m95128-r are no longer under development. test conditions changed for v ol and v oh in section table 14.: dc characteristics (m95128-w, device grade 3) . 27-jun-2006 7 figure 12: bus master and memory devices on the spi bus modified. so8n package specifications updated (see ta bl e 2 0 and figure 18 ). v process specified and a process replaced by p in table 22: ordering information scheme . table 23. document revision history (continued) date revision changes
m95128, m95128-w, m95128-r 41/41 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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